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A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values21st International Conference on Field Programmable Logic and Applications (FPL), Sep 2011, Chania, Greece. pp.273-276, ⟨10.1109/FPL.2011.55⟩
Communication dans un congrès
inria-00633200v1
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Plateforme matérielle–logicielle à bas coût pour l'émulation de fautesPoster de conférence hal-01346576v1 |
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Acceleration of a bioinformatics application using high-level synthesisOther [cs.OH]. École normale supérieure de Cachan - ENS Cachan, 2012. English. ⟨NNT : 2012DENS0019⟩
Thèse
tel-00847076v1
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Automatic synthesis of hardware accelerator from high-level specifications of physical layers for flexible radioNetworking and Internet Architecture [cs.NI]. Université de Rennes, 2014. English. ⟨NNT : 2014REN1S183⟩
Thèse
tel-01492963v1
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FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable RegionsFCCM - 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, United States. pp.30, ⟨10.1109/FCCM.2014.17⟩
Communication dans un congrès
hal-01100334v1
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A Domain-specific Language for Autonomic Managers in FPGA Reconfigurable ArchitecturesICAC 2018 - 15th IEEE International Conference on Autonomic Computing, Sep 2018, Trento, Italy. pp.1-10
Communication dans un congrès
hal-01868675v1
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An FPGA target for the StarPU heterogeneous runtime system13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (RECOSOC 2018), Jul 2018, Lille, France. pp.1-8
Communication dans un congrès
hal-01858951v1
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An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable SystemsACM Transactions on Design Automation of Electronic Systems, 2015, Vol. 21 Issue 1, Article No. 8, Nov. 2015 ., 21 (1), pp.Article No. 8
Article dans une revue
hal-01172123v1
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An FPGA-specific Approach to Floating-Point Accumulation and Sum-of-ProductsField-Programmable Technology, Dec 2008, Taipei, Taiwan
Communication dans un congrès
ensl-00268348v3
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FPGA-Specific Arithmetic Optimizations of Short-Latency Adders2011 International Conference on Field Programmable Logic and Applications (FPL), Sep 2011, Chania, Greece. pp.232 - 237, ⟨10.1109/FPL.2011.49⟩
Communication dans un congrès
ensl-00542389v1
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ROOM : reconfigurable object-oriented machines for specific applications[Research Report] RR-4588, INRIA. 2002
Rapport
inria-00071997v1
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Recherches de motifs et de similarités en bioinformatique : modélisations, solutions logicielles et matériellesMajecSTIC 2005 : Manifestation des Jeunes Chercheurs francophones dans les domaines des STIC, IRISA – IETR – LTSI, Nov 2005, Rennes/France, pp.18--37
Communication dans un congrès
inria-00001036v1
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Modular Multiplication for FPGA Implementation of the IDEA Block CipherRR-4558, INRIA. 2002
Rapport
inria-00072030v1
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Multiplication-addition modulaire: algorithmes itératifs et implantations sur FPGARR-4840, INRIA. 2003
Rapport
inria-00071745v1
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New Identities and Transformations for Hardware Power OperatorsAdvanced Signal Processing Algorithms, Architectures and Implementations XVI, Aug 2006, San Diego, California, U.S.A., pp.1-10 (631307), ⟨10.1117/12.676244⟩
Communication dans un congrès
lirmm-00125518v1
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Arithmetic Operators for Pairing-Based Cryptography[Research Report] LIP RR-2007-13, Laboratoire de l'informatique du parallélisme. 2007, 2+16p
Rapport
hal-02102042v1
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High-performance Elliptic Curve Cryptography by Using the CIOS Method for Modular MultiplicationCRiSIS 2016, Sep 2016, Roscoff, France
Communication dans un congrès
hal-01383162v1
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Automatic Generation of FPGA-Specific Pipelined AcceleratorsInternational Symposium on Applied Reconfigurable Computing (ARC'11), Mar 2011, Belfast, United Kingdom
Communication dans un congrès
ensl-00549682v1
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A flexible floating-point logarithm for reconfigurable computers2010
Pré-publication, Document de travail
ensl-00506122v1
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On-Line Arithmetic Based Reprogrammable Hardware Implementation of LVQ Neural Network for Alertness ClassificationInternational Journal of Computer Science and Network Security, 2008, 8 (3), pp.260-266
Article dans une revue
inria-00338767v1
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A Linux-Based Support for Developing Real-Time Applications on Heterogeneous Platforms with Dynamic FPGA ReconfigurationFuture Generation Computer Systems, 2022, 129, pp.125-140. ⟨10.1016/j.future.2021.11.007⟩
Article dans une revue
hal-03512476v1
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High-performance floating-point computing on reconfigurable circuitsOther [cs.OH]. Ecole normale supérieure de lyon - ENS LYON, 2011. English. ⟨NNT : 2011ENSL0656⟩
Thèse
tel-00654121v2
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Opérateurs itératifs de multiplication-addition modulaire pour FPGA[Rapport de recherche] RR-4937, LIP RR-2003-40, INRIA, LIP. 2003
Rapport
inria-00071642v1
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High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline ModelEDHPC 2023 - European Data Handling & Data Processing Conference, European Space Agency (ESA), Oct 2023, Juan-Les-Pins, France. pp.1-10
Communication dans un congrès
hal-04294305v1
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On the FPGA-based implementation of a flexible waveform from a high-level description: Application to LTE FFT case studyEAI International Conference on Cognitive Radio Oriented Wireless Networks (Crowncom16), May 2016, Grenoble, France
Communication dans un congrès
hal-01302652v1
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Simty: a Synthesizable General-Purpose SIMT Processor[Research Report] RR-8944, Inria Rennes Bretagne Atlantique. 2016
Rapport
hal-01351689v2
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Making Frugal Spatial Audio Systems Using Field-Programmable Gate ArraysProceedings of the 2023 New Interfaces for Musical Expression Conference, May 2023, Mexico City, Mexico
Communication dans un congrès
hal-04169228v1
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SMURF: Scalar Multiple-precision Unum Risc-V Floating-point Accelerator for Scientific ComputingCoNGA 2019 - Conference on Next-Generation Arithmetic, Mar 2019, Singapour, Singapore. pp.1-8, ⟨10.1145/3316279.3316280⟩
Communication dans un congrès
hal-02087098v1
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High-Speed Flow-Based Classification on FPGAInternational Journal of Network Management, 2014, 24 (4), pp.253-271. ⟨10.1002/nem.1863⟩
Article dans une revue
istex
hal-01058333v1
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Methodology and Tools for Energy-aware Task Mapping on Heterogeneous Multiprocessor ArchitecturesEmbedded Systems. Université de Rennes 1, 2017. English. ⟨NNT : ⟩
Thèse
tel-01672814v1
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